Ted Weatherford (Lin), VP Business Development and John Carney (Lin), Distinguished Engineer, SW Architecture of Xsight Labs, presented at a recent AI Infrastructure Field Day (AIIFD4, see video of their session here) I attended and thought they had a great way to solve the need for high speed/software defined networking (SDN) in modern data centers.
Turns out Xsight Labs is a fabless semiconductor company, specializing in SDN ASICs and currently have an X2 Switch ASIC and a E1 DPU ASIC out on the market today. They are the first vendor to have an 800Gbps DPU ASIC and their 12.8T X2 switch chip is focused on low power SDN for ToR, edge and extreme edge environments. Listen to the podcast to learn more.
Podcast: Play in new window | Download (Duration: 50:44 — 69.7MB) | Embed
Subscribe: Apple Podcasts | Spotify | RSS
Ted said there are 6 primary chips which make up AI data centers: GPU, CPU, NIC, Scale up networking switch, Scale out networking switch, & DPU chips. And there are maybe 20 semiconductor dev groups around the world capable of developing these. Their current monolithic die chips use the TSMC N5 process. While their networking X2 switch chip has been out in volume for a while now and is in its second generation, their E1 DPU chip is brand new.
We started discussing their X2 SDN switch chip. The X2 supports up to 128 ports/12.8T in 1RU (based on reference switch architecture) at under 200W and any port can configured to support 10G to 400G.
In addition to their switch form factor and power envelope, the X2’s programability is a major strength. They have over 3000 dedicated, “MAP” core CPUs or Harvard (separate instructions and data memory and access paths) core CPUs to process, in parallel, the data flows in and out of the chip plus separate parser cores. The 3072 MAP cores are allocated statically to 64 parallel packet forwarding engines and 64 data plane units and there’s a 64MB packet buffer shared across all ports.
They have had a couple of PoCs where customers managed to code X2 switch support for their application in a matter of weeks (days maybe).
Moving on to the E1 DPU chip, the story gets even more interesting. Traditionally, DPUs have had a hybrid architecture where the data path processing is done in parallel cores and the management processing in a handful of RISC cores requiring clients to code in multiple architectural environments. Xsight labs took a different tack.
The E1 has up to 64 N2 ARM cores and can literally run Linux or other OSs (at the same time) to support DPU processing. (Btw, the latest gen Apple M5 CPU only has 8 fast ARM cores and 4 slow ARM cores). On the server side of the DPU, it supports up to 40 PCIe Gen5 lanes and on the ethernet side 1-800Gbps port, 2-400Gbps ports, 4-200Gbps ports, etc..
The E1 also supports 4 DDR5 5200 MHz memory interfaces which means E1 can support TBs of memory!? John went into the software architecture a bit more on our podcast than at AIIFD4 and said it had 32MB of system cache.
John said main memory would mostly be used to host static/slowly changing databases and tables. Actual instructions to support DPU IO would all reside in ARM l1-l2-l3 instruction caches during processing. The E1 operates the 800G port at line speed within 75W of power.
At AIIFD4, they discussed their SONiC DASH benchmark VNET to VNET scenario results. SONiC DASH is an open source project started by Microsoft, used to assess smart switches under cloud service provider workloads. There are many levels for the SONiC DASH benchmark and their E1 DPU-X2 network (reference architecture) smart switch was the first smart switch to sustain Hero800 performance (800Gbps link support) using only a single DPU. This means their E1 DPU-X2 switch processed in excess of 14M TCP connections/second for over a minute and a half, all while sustaining over 120M TCP&UDP background data flows.
As for customer wins, Ted mentioned each SpaceX Starlink V3 satellite uses multiple X2 chips and that the Open Flash Platform (OFP) organization is currently implementing an NFS server using a single E1 DPU and PBs of flash in a single sled. This means OFP is mapping a Linux file system across all the flash in the sled and presenting it as a NFS storage server out the front end. No server required…
Ted Weatherford, VP Business Development, Xsight Labs
Ted Weatherford is Vice President of Business Development at Xsight Labs, where he was hired to build out a commercial team, discover and close first strategic customer engagements, manages HW and SW partner ecosystems, and contribute to go-to-market activities for the company’s products and engineering services.
Ted brings over 30 years of experience in product line management, business development, and strategic marketing in the semiconductor industry. Over his career, his work has contributed to hundreds of chip design-wins globally and generated more than $2 billion in revenue for leading merchant silicon suppliers including BRCM, INTL, CRDO, MTK, MRVL and many others
John Carney, Distinguished Engineer, Software Architecture, Xsight Labs
John is a Distinguished Engineer at Xsight Labs, focused on software architecture for Xsight’s E-series DPU products.
Prior to Xsight, John held hardware and software technical leadership roles at Broadcom, Cisco and Juniper.
John is an expert in high-performance networking data planes.